May 2020 Archives by author

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Starting: Fri May 1 03:09:45 BST 2020
Ending: Sun May 31 23:14:21 BST 2020
Messages: 1349

• [libre-riscv-dev] Fwd: power-gem5   lkcl .
• [libre-riscv-dev] [OpenPOWER-HDL-Cores] little-endian only power cores and spec compliance   Hugh Blemings
• [libre-riscv-dev] Verilog book   Hendrik Boom
• [libre-riscv-dev] Verilog book   Hendrik Boom
• [libre-riscv-dev] PowerISA 3.1 (Power10) spec released   Hendrik Boom
• [libre-riscv-dev] PowerISA 3.1 (Power10) spec released   Hendrik Boom
• [libre-riscv-dev] [OpenPOWER-HDL-Cores] little-endian only power cores and spec compliance   Benjamin Herrenschmidt
• [libre-riscv-dev] Finished Scoreboard   Immanuel, Yehowshua U
• [libre-riscv-dev] PowerISA 3.1 (Power10) spec released   Lauri Kasanen
• [libre-riscv-dev] PowerISA 3.1 (Power10) spec released   Lauri Kasanen
• [libre-riscv-dev] PowerISA 3.1 (Power10) spec released   Lauri Kasanen
• [libre-riscv-dev] PowerISA 3.1 (Power10) spec released   Lauri Kasanen
• [libre-riscv-dev] PowerISA 3.1 (Power10) spec released   Lauri Kasanen
• [libre-riscv-dev] more compatible alternative to BE instructions on LE processor   Lauri Kasanen
• [libre-riscv-dev] load/store execution queue idea   Luke Kenneth Casson Leighton
• [libre-riscv-dev] sun opensparc t2   Luke Kenneth Casson Leighton
• [libre-riscv-dev] sum-addressed decoder   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Documenting the SOC tree Repository   Luke Kenneth Casson Leighton
• [libre-riscv-dev] GItlab For SOC repo   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Documenting the SOC tree Repository   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Needed Subset of POWER   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Documenting the SOC tree Repository   Luke Kenneth Casson Leighton
• [libre-riscv-dev] experimental code & monorepo   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Merging Repositories and Auto-Generating Static Documentation   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Merging Repositories and Auto-Generating Static Documentation   Luke Kenneth Casson Leighton
• [libre-riscv-dev] global network of developers   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Merging Repositories and Auto-Generating Static Documentation   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Merging Repositories and Auto-Generating Static Documentation   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily status update 05may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] global network of developers   Luke Kenneth Casson Leighton
• [libre-riscv-dev] global network of developers   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily status update 05may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily status update 05may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] global network of developers   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Finished Scoreboard   Luke Kenneth Casson Leighton
• [libre-riscv-dev] CORDIC importance   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily status update 05may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily status update 05may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily status update 05may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily status update 05may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] crowdsupply update progress   Luke Kenneth Casson Leighton
• [libre-riscv-dev] crowdsupply update progress   Luke Kenneth Casson Leighton
• [libre-riscv-dev] website title   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Finished Scoreboard   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Finished Scoreboard   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily status update 05may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 06may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] global network of developers   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily status update 05may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 06may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 06may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 06may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 06may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 06may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban 07may2020 update   Luke Kenneth Casson Leighton
• [libre-riscv-dev] 4 Simulators?   Luke Kenneth Casson Leighton
• [libre-riscv-dev] 4 Simulators?   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban 07may2020 update   Luke Kenneth Casson Leighton
• [libre-riscv-dev] 4 Simulators?   Luke Kenneth Casson Leighton
• [libre-riscv-dev] MMU + TLB idea   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban 07may2020 update   Luke Kenneth Casson Leighton
• [libre-riscv-dev] nMigen Hierachical Issues   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban 07may2020 update   Luke Kenneth Casson Leighton
• [libre-riscv-dev] minimum viable ASIC   Luke Kenneth Casson Leighton
• [libre-riscv-dev] minimum viable ASIC   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban 07may2020 update   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 08mar2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 08mar2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban 07may2020 update   Luke Kenneth Casson Leighton
• [libre-riscv-dev] minimum viable ASIC   Luke Kenneth Casson Leighton
• [libre-riscv-dev] minimum viable ASIC   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Pinout, interfaces, Rudi, and Raptor   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 08mar2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 08mar2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 08mar2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 08mar2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] HDL_Workflow clarification   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)   Luke Kenneth Casson Leighton
• [libre-riscv-dev] minimum viable ASIC   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 08mar2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 08mar2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 08mar2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 08mar2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 08mar2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 08may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] note on memory operation requirements for linux   Luke Kenneth Casson Leighton
• [libre-riscv-dev] LD/ST CompUnit "working"   Luke Kenneth Casson Leighton
• [libre-riscv-dev] spinlocks considered harmful   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 08may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] pinmux to generate interfaces (with no pinmux)   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Pinout, interfaces, Rudi, and Raptor   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 09may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] insights about the selection of the design and architecture   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Handling Interrupts   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 11may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] PowerISA 3.1 (Power10) spec released   Luke Kenneth Casson Leighton
• [libre-riscv-dev] PowerISA 3.1 (Power10) spec released   Luke Kenneth Casson Leighton
• [libre-riscv-dev] PowerISA 3.1 (Power10) spec released   Luke Kenneth Casson Leighton
• [libre-riscv-dev] ppc-dev linux patch support for microwatt!   Luke Kenneth Casson Leighton
• [libre-riscv-dev] ppc-dev linux patch support for microwatt!   Luke Kenneth Casson Leighton
• [libre-riscv-dev] ppc-dev linux patch support for microwatt!   Luke Kenneth Casson Leighton
• [libre-riscv-dev] ppc-dev linux patch support for microwatt!   Luke Kenneth Casson Leighton
• [libre-riscv-dev] ppc-dev linux patch support for microwatt!   Luke Kenneth Casson Leighton
• [libre-riscv-dev] ppc-dev linux patch support for microwatt!   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Power memory fences and icache handling   Luke Kenneth Casson Leighton
• [libre-riscv-dev] little-endian only power cores and spec compliance   Luke Kenneth Casson Leighton
• [libre-riscv-dev] PowerISA 3.1 (Power10) spec released   Luke Kenneth Casson Leighton
• [libre-riscv-dev] PowerISA 3.1 (Power10) spec released   Luke Kenneth Casson Leighton
• [libre-riscv-dev] PowerISA 3.1 (Power10) spec released   Luke Kenneth Casson Leighton
• [libre-riscv-dev] little-endian only power cores and spec compliance   Luke Kenneth Casson Leighton
• [libre-riscv-dev] learning from a failed business   Luke Kenneth Casson Leighton
• [libre-riscv-dev] little-endian only power cores and spec compliance   Luke Kenneth Casson Leighton
• [libre-riscv-dev] PowerISA 3.1 (Power10) spec released   Luke Kenneth Casson Leighton
• [libre-riscv-dev] PowerISA 3.1 (Power10) spec released   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 11may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 12may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] PowerISA 3.1 (Power10) spec released   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 12may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 12may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] PowerISA 3.1 (Power10) spec released   Luke Kenneth Casson Leighton
• [libre-riscv-dev] more compatible alternative to BE instructions on LE processor   Luke Kenneth Casson Leighton
• [libre-riscv-dev] more compatible alternative to BE instructions on LE processor   Luke Kenneth Casson Leighton
• [libre-riscv-dev] [OpenPOWER-HDL-Cores] little-endian only power cores and spec compliance   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 13may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 13may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 13may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog   Luke Kenneth Casson Leighton
• [libre-riscv-dev] note on memory operation requirements for linux   Luke Kenneth Casson Leighton
• [libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 13may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] popcount and parity   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 14may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 14may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 14may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 14may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] virtual coffee openpower, in 50 minutes   Luke Kenneth Casson Leighton
• [libre-riscv-dev] quick write-up about microwatt and Libre-SOC HDL   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 14may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 14may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 14may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 14may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 14may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 14may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 14may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 15may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] marketnext online call, earlier today   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Power ISA v3.1 bug - parityw   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Introduction and Questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Introduction and Questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Introduction and Questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Introduction and Questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Introduction and Questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Introduction and Questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Introduction and Questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Introduction and Questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Introduction and Questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 16may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Scoreboard vs Tomasulo   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Scoreboard vs Tomasulo   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Scoreboard vs Tomasulo   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Scoreboard vs Tomasulo   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Scoreboard vs Tomasulo   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Scoreboard vs Tomasulo   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Scoreboard vs Tomasulo   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 16may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Priority Encoder   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Scoreboard vs Tomasulo   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Priority Encoder   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Scoreboard vs Tomasulo   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Introduction and Questions   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Scoreboard vs Tomasulo   Luke Kenneth Casson Leighton
• [libre-riscv-dev] LD/ST Comp Unit FSM (was: Re: Scoreboard vs Tomasulo)   Luke Kenneth Casson Leighton
• [libre-riscv-dev] LD/ST Comp Unit FSM (was: Re: Scoreboard vs Tomasulo)   Luke Kenneth Casson Leighton
• [libre-riscv-dev] LD/ST Comp Unit FSM (was: Re: Scoreboard vs Tomasulo)   Luke Kenneth Casson Leighton
• [libre-riscv-dev] LD/ST Comp Unit FSM (was: Re: Scoreboard vs Tomasulo)   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 18may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Avoiding Spectre or Meltdown   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Rough timing estimate in yosys   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Rough timing estimate in yosys   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 18may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] [Bug 209] spectre-proof speculative execution   Luke Kenneth Casson Leighton
• [libre-riscv-dev] closing git https access bug   Luke Kenneth Casson Leighton
• [libre-riscv-dev] [Bug 266] deploy git commit-signing and tag-signing   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 19may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 19may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Tomasulo and Scoreboards   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Tomasulo and Scoreboards   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 19may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 19may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] priority encoder replacement   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 19may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 20may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 20may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 20may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] RISCV-V Extension   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)   Luke Kenneth Casson Leighton
• [libre-riscv-dev] monorepo   Luke Kenneth Casson Leighton
• [libre-riscv-dev] monorepo   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 20may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 21may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 21may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 21may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 21may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 21may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 22may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 22may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 22may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 22may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 22may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] dns entries for talos server & server maintenance   Luke Kenneth Casson Leighton
• [libre-riscv-dev] dns entries for talos server & server maintenance   Luke Kenneth Casson Leighton
• [libre-riscv-dev] dns entries for talos server & server maintenance   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 22may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] dns entries for talos server & server maintenance   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 22may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 22may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Priority Encoder for Cesar   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 23may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 23may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Function Units "patch-up" linking to Comp Unit code   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 23may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 23may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 23may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 23may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 23may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 23may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 23may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 23may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 23may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 23may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 23may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 23may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 23may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Fwd: [OpenPOWER-HDL-Cores] POWER9 ISA opcode usage statistics   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 24may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] idea for testing pipelines   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 24may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 25may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 25may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 25may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 25may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 25may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 25may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 25may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 25may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 26may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 26may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 26may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 26may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 26may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 26may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 26may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 26may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 26may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] funny article about Rust and technical interviews   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 27may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] POWER9 formal correctness proofs collaboration   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 27may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Power ISA v3.1 bug - parityw   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 28may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] openpower virtual coffee call 28may2020, 90 minutes time   Luke Kenneth Casson Leighton
• [libre-riscv-dev] openpower virtual coffee call 28may2020, 90 minutes time   Luke Kenneth Casson Leighton
• [libre-riscv-dev] openpower virtual coffee call 28may2020, 90 minutes time   Luke Kenneth Casson Leighton
• [libre-riscv-dev] openpower virtual coffee call 28may2020, 90 minutes time   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 28may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 28may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 28may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Rough Architectural Sketch   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 29may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 29may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 29may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 29may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 29may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] EU residency / businesses   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 30may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 30may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Request for Scoreboard and Functional Units Update   Luke Kenneth Casson Leighton
• [libre-riscv-dev] Request for Scoreboard and Functional Units Update   Luke Kenneth Casson Leighton
• [libre-riscv-dev] MultiCompUnit- ALU interaction. was: daily kan-ban update 30may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] MultiCompUnit- ALU interaction. was: daily kan-ban update 30may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] MultiCompUnit- ALU interaction. was: daily kan-ban update 30may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 30may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 31may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 31may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] daily kan-ban update 31may2020   Luke Kenneth Casson Leighton
• [libre-riscv-dev] load/store execution queue idea   Jacob Lifshay
• [libre-riscv-dev] sum-addressed decoder   Jacob Lifshay
• [libre-riscv-dev] experimental code & monorepo   Jacob Lifshay
• [libre-riscv-dev] experimental code & monorepo   Jacob Lifshay
• [libre-riscv-dev] load/store execution queue idea   Jacob Lifshay
• [libre-riscv-dev] daily status update 05may2020   Jacob Lifshay
• [libre-riscv-dev] website title   Jacob Lifshay
• [libre-riscv-dev] crowdsupply update progress   Jacob Lifshay
• [libre-riscv-dev] crowdsupply update progress   Jacob Lifshay
• [libre-riscv-dev] daily kan-ban update 06may2020   Jacob Lifshay
• [libre-riscv-dev] 4 Simulators?   Jacob Lifshay
• [libre-riscv-dev] 4 Simulators?   Jacob Lifshay
• [libre-riscv-dev] daily kan-ban 07may2020 update   Jacob Lifshay
• [libre-riscv-dev] note on memory operation requirements for linux   Jacob Lifshay
• [libre-riscv-dev] daily kan-ban update 08mar2020   Jacob Lifshay
• [libre-riscv-dev] daily kan-ban update 08may2020   Jacob Lifshay
• [libre-riscv-dev] spinlocks considered harmful   Jacob Lifshay
• [libre-riscv-dev] LD/ST CompUnit "working"   Jacob Lifshay
• [libre-riscv-dev] Power memory fences and icache handling   Jacob Lifshay
• [libre-riscv-dev] learning from a failed business   Jacob Lifshay
• [libre-riscv-dev] PowerISA 3.1 (Power10) spec released   Jacob Lifshay
• [libre-riscv-dev] PowerISA 3.1 (Power10) spec released   Jacob Lifshay
• [libre-riscv-dev] little-endian only power cores and spec compliance   Jacob Lifshay
• [libre-riscv-dev] little-endian only power cores and spec compliance   Jacob Lifshay
• [libre-riscv-dev] little-endian only power cores and spec compliance   Jacob Lifshay
• [libre-riscv-dev] little-endian only power cores and spec compliance   Jacob Lifshay
• [libre-riscv-dev] more compatible alternative to BE instructions on LE processor   Jacob Lifshay
• [libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog   Jacob Lifshay
• [libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog   Jacob Lifshay
• [libre-riscv-dev] daily kan-ban update 14may2020   Jacob Lifshay
• [libre-riscv-dev] Introduction and Questions   Jacob Lifshay
• [libre-riscv-dev] Avoiding Spectre or Meltdown   Jacob Lifshay
• [libre-riscv-dev] closing git https access bug   Jacob Lifshay
• [libre-riscv-dev] [Bug 266] deploy git commit-signing and tag-signing   Jacob Lifshay
• [libre-riscv-dev] daily kan-ban update 19may2020   Jacob Lifshay
• [libre-riscv-dev] priority encoder replacement   Jacob Lifshay
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   Jacob Lifshay
• [libre-riscv-dev] monorepo   Jacob Lifshay
• [libre-riscv-dev] daily kan-ban update 21may2020   Jacob Lifshay
• [libre-riscv-dev] openpower meeting starting shortly   Jacob Lifshay
• [libre-riscv-dev] daily kan-ban update 22may2020   Jacob Lifshay
• [libre-riscv-dev] dns entries for talos server & server maintenance   Jacob Lifshay
• [libre-riscv-dev] dns entries for talos server & server maintenance   Jacob Lifshay
• [libre-riscv-dev] daily kan-ban update 25may2020   Jacob Lifshay
• [libre-riscv-dev] daily kan-ban update 26may2020   Jacob Lifshay
• [libre-riscv-dev] funny article about Rust and technical interviews   Jacob Lifshay
• [libre-riscv-dev] funny article about Rust and technical interviews   Jacob Lifshay
• [libre-riscv-dev] daily kan-ban update 28may2020   Jacob Lifshay
• [libre-riscv-dev] daily kan-ban update 29may2020   Jacob Lifshay
• [libre-riscv-dev] [OpenPOWER-HDL-Cores] Power ISA v3.1 bug - parityw   Paul Mackerras
• [libre-riscv-dev] [OpenPOWER-HDL-Cores] Power ISA v3.1 bug - parityw   Paul Mackerras
• [libre-riscv-dev] daily kan-ban update 08mar2020   Michael N
• [libre-riscv-dev] CORDIC importance   Michael Nolan
• [libre-riscv-dev] daily status update 05may2020   Michael Nolan
• [libre-riscv-dev] daily status update 05may2020   Michael Nolan
• [libre-riscv-dev] daily kan-ban update 06may2020   Michael Nolan
• [libre-riscv-dev] 4 Simulators?   Michael Nolan
• [libre-riscv-dev] daily kan-ban 07may2020 update   Michael Nolan
• [libre-riscv-dev] MMU + TLB idea   Michael Nolan
• [libre-riscv-dev] daily kan-ban update 08mar2020   Michael Nolan
• [libre-riscv-dev] daily kan-ban update 08mar2020   Michael Nolan
• [libre-riscv-dev] daily kan-ban update 08mar2020   Michael Nolan
• [libre-riscv-dev] daily kan-ban update 11may2020   Michael Nolan
• [libre-riscv-dev] daily kan-ban update 12may2020   Michael Nolan
• [libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog   Michael Nolan
• [libre-riscv-dev] daily kan-ban update 14may2020   Michael Nolan
• [libre-riscv-dev] daily kan-ban update 14may2020   Michael Nolan
• [libre-riscv-dev] Power ISA v3.1 bug - parityw   Michael Nolan
• [libre-riscv-dev] daily kan-ban update 16may2020   Michael Nolan
• [libre-riscv-dev] Rough timing estimate in yosys   Michael Nolan
• [libre-riscv-dev] daily kan-ban update 19may2020   Michael Nolan
• [libre-riscv-dev] daily kan-ban update 20may2020   Michael Nolan
• [libre-riscv-dev] daily kan-ban update 21may2020   Michael Nolan
• [libre-riscv-dev] daily kan-ban update 22may2020   Michael Nolan
• [libre-riscv-dev] daily kan-ban update 23may2020   Michael Nolan
• [libre-riscv-dev] daily kan-ban update 25may2020   Michael Nolan
• [libre-riscv-dev] daily kan-ban update 26may2020   Michael Nolan
• [libre-riscv-dev] daily kan-ban update 26may2020   Michael Nolan
• [libre-riscv-dev] daily status update 05may2020   Tobias Platen
• [libre-riscv-dev] daily kan-ban update 06may2020   Tobias Platen
• [libre-riscv-dev] daily kan-ban 07may2020 update   Tobias Platen
• [libre-riscv-dev] 4 Simulators?   Tobias Platen
• [libre-riscv-dev] daily kan-ban update 12may2020   Tobias Platen
• [libre-riscv-dev] daily kan-ban update 13may2020   Tobias Platen
• [libre-riscv-dev] daily kan-ban update 13may2020   Tobias Platen
• [libre-riscv-dev] daily kan-ban update 14may2020   Tobias Platen
• [libre-riscv-dev] daily kan-ban update 14may2020   Tobias Platen
• [libre-riscv-dev] daily kan-ban update 18may2020   Tobias Platen
• [libre-riscv-dev] daily kan-ban update 19may2020   Tobias Platen
• [libre-riscv-dev] daily kan-ban update 21may2020   Tobias Platen
• [libre-riscv-dev] daily kan-ban update 22may2020   Tobias Platen
• [libre-riscv-dev] daily kan-ban update 23may2020   Tobias Platen
• [libre-riscv-dev] daily kan-ban update 24may2020   Tobias Platen
• [libre-riscv-dev] daily kan-ban update 25may2020   Tobias Platen
• [libre-riscv-dev] daily kan-ban update 26may2020   Tobias Platen
• [libre-riscv-dev] daily kan-ban update 27may2020   Tobias Platen
• [libre-riscv-dev] daily kan-ban update 31may2020   Tobias Platen
• [libre-riscv-dev] daily status update 05may2020   Cole Poirier
• [libre-riscv-dev] daily status update 05may2020   Cole Poirier
• [libre-riscv-dev] HDL_Workflow clarification   Cole Poirier
• [libre-riscv-dev] HDL_Workflow clarification   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 13may2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 14may2020   Cole Poirier
• [libre-riscv-dev] quick write-up about microwatt and Libre-SOC HDL   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 14may2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 15may2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 16may2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 19may2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 20may2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 20may2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 21may2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 22may2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 22may2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 23may2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 23may2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 23may2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 23may2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 23may2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 23may2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 23may2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 25may2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 25may2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 25may2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 25may2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 26may2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 26may2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 26may2020   Cole Poirier
• [libre-riscv-dev] funny article about Rust and technical interviews   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 27may2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 28may2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 28may2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 28may2020   Cole Poirier
• [libre-riscv-dev] Request for Scoreboard and Functional Units Update   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 30may2020   Cole Poirier
• [libre-riscv-dev] daily kan-ban update 30may2020   Cole Poirier
• [libre-riscv-dev] Introduction and Questions   Jeremy Singher
• [libre-riscv-dev] Introduction and Questions   Jeremy Singher
• [libre-riscv-dev] Introduction and Questions   Jeremy Singher
• [libre-riscv-dev] Introduction and Questions   Jeremy Singher
• [libre-riscv-dev] Introduction and Questions   Jeremy Singher
• [libre-riscv-dev] Introduction and Questions   Jeremy Singher
• [libre-riscv-dev] Scoreboard vs Tomasulo   Jeremy Singher
• [libre-riscv-dev] Introduction and Questions   Jeremy Singher
• [libre-riscv-dev] Scoreboard vs Tomasulo   Jeremy Singher
• [libre-riscv-dev] LD/ST Comp Unit FSM (was: Re: Scoreboard vs Tomasulo)   Cesar Strauss
• [libre-riscv-dev] LD/ST Comp Unit FSM (was: Re: Scoreboard vs Tomasulo)   Cesar Strauss
• [libre-riscv-dev] LD/ST Comp Unit FSM (was: Re: Scoreboard vs Tomasulo)   Cesar Strauss
• [libre-riscv-dev] daily kan-ban update 19may2020   Cesar Strauss
• [libre-riscv-dev] daily kan-ban update 22may2020   Cesar Strauss
• [libre-riscv-dev] daily kan-ban update 22may2020   Cesar Strauss
• [libre-riscv-dev] daily kan-ban update 22may2020   Cesar Strauss
• [libre-riscv-dev] Priority Encoder for Cesar   Cesar Strauss
• [libre-riscv-dev] daily kan-ban update 23may2020   Cesar Strauss
• [libre-riscv-dev] daily kan-ban update 25may2020   Cesar Strauss
• [libre-riscv-dev] daily kan-ban update 26may2020   Cesar Strauss
• [libre-riscv-dev] daily kan-ban update 29may2020   Cesar Strauss
• [libre-riscv-dev] daily kan-ban 07may2020 update   Staf Verhaegen
• [libre-riscv-dev] minimum viable ASIC   Staf Verhaegen
• [libre-riscv-dev] daily kan-ban 07may2020 update   Staf Verhaegen
• [libre-riscv-dev] minimum viable ASIC   Staf Verhaegen
• [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)   Staf Verhaegen
• [libre-riscv-dev] daily kan-ban update 08mar2020   Staf Verhaegen
• [libre-riscv-dev] minimum viable ASIC   Staf Verhaegen
• [libre-riscv-dev] Pinout, interfaces, Rudi, and Raptor   Staf Verhaegen
• [libre-riscv-dev] Introduction and Questions   Staf Verhaegen
• [libre-riscv-dev] Introduction and Questions   Staf Verhaegen
• [libre-riscv-dev] Introduction and Questions   Staf Verhaegen
• [libre-riscv-dev] daily kan-ban update 18may2020   Staf Verhaegen
• [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)   Staf Verhaegen
• [libre-riscv-dev] daily kan-ban update 08mar2020   Alain D D Williams
• [libre-riscv-dev] openpower virtual coffee call 28may2020, 90 minutes time   Alain D D Williams
• [libre-riscv-dev] openpower virtual coffee call 28may2020, 90 minutes time   Alain D D Williams
• [libre-riscv-dev] daily kan-ban update 28may2020   Alain D D Williams
• [libre-riscv-dev] daily kan-ban update 28may2020   Alain D D Williams
• [libre-riscv-dev] Documenting the SOC tree Repository   Yehowshua
• [libre-riscv-dev] Documenting the SOC tree Repository   Yehowshua
• [libre-riscv-dev] GItlab For SOC repo   Yehowshua
• [libre-riscv-dev] GItlab For SOC repo   Yehowshua
• [libre-riscv-dev] Documenting the SOC tree Repository   Yehowshua
• [libre-riscv-dev] Needed Subset of POWER   Yehowshua
• [libre-riscv-dev] Documenting the SOC tree Repository   Yehowshua
• [libre-riscv-dev] Documenting the SOC tree Repository   Yehowshua
• [libre-riscv-dev] Merging Repositories and Auto-Generating Static Documentation   Yehowshua
• [libre-riscv-dev] Merging Repositories and Auto-Generating Static Documentation   Yehowshua
• [libre-riscv-dev] daily status update 05may2020   Yehowshua
• [libre-riscv-dev] daily status update 05may2020   Yehowshua
• [libre-riscv-dev] global network of developers   Yehowshua
• [libre-riscv-dev] global network of developers   Yehowshua
• [libre-riscv-dev] Finished Scoreboard   Yehowshua
• [libre-riscv-dev] daily kan-ban update 06may2020   Yehowshua
• [libre-riscv-dev] 4 Simulators?   Yehowshua
• [libre-riscv-dev] 4 Simulators?   Yehowshua
• [libre-riscv-dev] 4 Simulators?   Yehowshua
• [libre-riscv-dev] daily kan-ban 07may2020 update   Yehowshua
• [libre-riscv-dev] nMigen Hierachical Issues   Yehowshua
• [libre-riscv-dev] daily kan-ban 07may2020 update   Yehowshua
• [libre-riscv-dev] minimum viable ASIC   Yehowshua
• [libre-riscv-dev] minimum viable ASIC   Yehowshua
• [libre-riscv-dev] minimum viable ASIC   Yehowshua
• [libre-riscv-dev] minimum viable ASIC   Yehowshua
• [libre-riscv-dev] minimum viable ASIC   Yehowshua
• [libre-riscv-dev] daily kan-ban update 08mar2020   Yehowshua
• [libre-riscv-dev] Pinout, interfaces, Rudi, and Raptor   Yehowshua
• [libre-riscv-dev] minimum viable ASIC   Yehowshua
• [libre-riscv-dev] daily kan-ban update 08mar2020   Yehowshua
• [libre-riscv-dev] daily kan-ban update 08may2020   Yehowshua
• [libre-riscv-dev] daily kan-ban update 08may2020   Yehowshua
• [libre-riscv-dev] Pinout, interfaces, Rudi, and Raptor   Yehowshua
• [libre-riscv-dev] Handling Interrupts   Yehowshua
• [libre-riscv-dev] PowerISA 3.1 (Power10) spec released   Yehowshua
• [libre-riscv-dev] ppc-dev linux patch support for microwatt!   Yehowshua
• [libre-riscv-dev] ppc-dev linux patch support for microwatt!   Yehowshua
• [libre-riscv-dev] ppc-dev linux patch support for microwatt!   Yehowshua
• [libre-riscv-dev] ppc-dev linux patch support for microwatt!   Yehowshua
• [libre-riscv-dev] daily kan-ban update 12may2020   Yehowshua
• [libre-riscv-dev] daily kan-ban update 14may2020   Yehowshua
• [libre-riscv-dev] Introduction and Questions   Yehowshua
• [libre-riscv-dev] Introduction and Questions   Yehowshua
• [libre-riscv-dev] Introduction and Questions   Yehowshua
• [libre-riscv-dev] Introduction and Questions   Yehowshua
• [libre-riscv-dev] Introduction and Questions   Yehowshua
• [libre-riscv-dev] Introduction and Questions   Yehowshua
• [libre-riscv-dev] Introduction and Questions   Yehowshua
• [libre-riscv-dev] Scoreboard vs Tomasulo   Yehowshua
• [libre-riscv-dev] Scoreboard vs Tomasulo   Yehowshua
• [libre-riscv-dev] Priority Encoder   Yehowshua
• [libre-riscv-dev] Priority Encoder   Yehowshua
• [libre-riscv-dev] Scoreboard vs Tomasulo   Yehowshua
• [libre-riscv-dev] Avoiding Spectre or Meltdown   Yehowshua
• [libre-riscv-dev] [Bug 209] spectre-proof speculative execution   Yehowshua
• [libre-riscv-dev] RISCV-V Extension   Yehowshua
• [libre-riscv-dev] openpower virtual coffee call 28may2020, 90 minutes time   Yehowshua
• [libre-riscv-dev] openpower virtual coffee call 28may2020, 90 minutes time   Yehowshua
• [libre-riscv-dev] daily kan-ban update 28may2020   Yehowshua
• [libre-riscv-dev] Rough Architectural Sketch   Yehowshua
• [libre-riscv-dev] daily kan-ban update 29may2020   Yehowshua
• [libre-riscv-dev] daily kan-ban update 29may2020   Yehowshua
• [libre-riscv-dev] Request for Scoreboard and Functional Units Update   Yehowshua
• [libre-riscv-dev] Request for Scoreboard and Functional Units Update   Yehowshua
• [libre-riscv-dev] MultiCompUnit- ALU interaction. was: daily kan-ban update 30may2020   Yehowshua
• [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)   whygee at f-cpu.org
• [libre-riscv-dev] [Bug 296] New: idea: cyclic buffer between FUs and register file   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 297] New: nmutil "flatten" function already exists   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 297] nmutil "flatten" function already exists   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 298] New: consider using sum-addressed decoder in L1 cache (maybe also L1 I cache)   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 297] nmutil "flatten" function already exists   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 297] nmutil "flatten" function already exists   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 297] nmutil "flatten" function already exists   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 297] nmutil "flatten" function already exists   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 297] nmutil "flatten" function already exists   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 298] consider using sum-addressed decoder in L1 cache (maybe also L1 I cache)   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 299] New: improve memory clash detection   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 300] New: Documentation for the SOC   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 300] Documentation for the SOC   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 301] New: design a micro-op subsystem that works with scoreboards   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 302] New: create a list of exception types for LD/ST operations in POWER   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 302] create a list of exception types for LD/ST operations in POWER   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 300] Documentation for the SOC   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 303] New: define peripheral set for 180nm ASIC   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 304] New: Define minimum viable interface set for 180nm ASIC   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 304] Define minimum viable interface set for 180nm ASIC   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 304] Define minimum viable interface set for 180nm ASIC   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] New: Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 306] New: Formal Correctness Proof for ALU pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 198] Formal correctness proofs are needed for low-level libraries in LibreSOC   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 307] New: look at installing a kan-ban board on top of bugzilla   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 307] look at installing a kan-ban board on top of bugzilla   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 307] look at installing a kan-ban board on top of bugzilla   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 307] look at installing a kan-ban board on top of bugzilla   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 70] evaluate Bus Architectures   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 70] evaluate Bus Architectures   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 303] define peripheral set for 180nm ASIC   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 303] define peripheral set for 180nm ASIC   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 303] define peripheral set for 180nm ASIC   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 304] Define minimum viable interface set for 180nm ASIC   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 304] Define minimum viable interface set for 180nm ASIC   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 304] Define minimum viable interface set for 180nm ASIC   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 291] HDL Workflow and Coriolis2 chroot automated setup scripts   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 307] look at installing a kan-ban board on top of bugzilla   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 307] look at installing a kan-ban board on top of bugzilla   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 307] look at installing a kan-ban board on top of bugzilla   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 291] HDL Workflow and Coriolis2 chroot automated setup scripts   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 291] HDL Workflow and Coriolis2 chroot automated setup scripts   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 291] HDL Workflow and Coriolis2 chroot automated setup scripts   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 291] HDL Workflow and Coriolis2 chroot automated setup scripts   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 291] HDL Workflow and Coriolis2 chroot automated setup scripts   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 291] HDL Workflow and Coriolis2 chroot automated setup scripts   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 308] New: POWER variable-length encoding scheme needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 238] POWER Compressed Formal Standard writeup   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 308] POWER variable-length encoding scheme needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 309] New: investigate OpenTITAN   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 309] investigate OpenTITAN   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 309] investigate OpenTITAN   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 309] investigate OpenTITAN   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 291] HDL Workflow and Coriolis2 chroot automated setup scripts   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 310] New: Function Units to cover multiple tasks   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 310] Function Units to cover multiple tasks   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 310] Function Units to cover multiple tasks   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 310] Function Units to cover multiple tasks   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 311] New: countzero function for Logic Pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 311] countzero function for Logic Pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 311] countzero function for Logic Pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 311] countzero function for Logic Pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 311] countzero function for Logic Pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 311] countzero function for Logic Pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 312] New: Formal Correctness Proof for CountZero needed (basically PriorityEncoder)   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 311] countzero function for Logic Pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 312] Formal Correctness Proof for CountZero needed (basically PriorityEncoder)   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 312] Formal Correctness Proof for CountZero needed (basically PriorityEncoder)   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 312] Formal Correctness Proof for CountZero needed (basically PriorityEncoder)   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 198] Formal correctness proofs are needed for low-level libraries in LibreSOC   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] New: Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 314] New: Create Condition Register pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 314] Create Condition Register pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 314] Create Condition Register pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 315] New: SPR Pipeline needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 314] Create Condition Register pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 315] SPR Pipeline needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 315] SPR Pipeline needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] New: bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 291] HDL Workflow and Coriolis2 chroot automated setup scripts   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 314] Create Condition Register pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 314] Create Condition Register pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 314] Create Condition Register pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 314] Create Condition Register pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 314] Create Condition Register pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 314] Create Condition Register pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 314] Create Condition Register pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 314] Create Condition Register pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 314] Create Condition Register pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 314] Create Condition Register pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 314] Create Condition Register pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 314] Create Condition Register pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 314] Create Condition Register pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 314] Create Condition Register pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 317] New: multi-bit dependency tracking of split (ganged) regfile ports   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 314] Create Condition Register pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 317] multi-bit dependency tracking of split (ganged) regfile ports   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 314] Create Condition Register pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] New: fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 319] New: POWER9 setting carry (and other) XER flags   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 319] POWER9 setting carry (and other) XER flags   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 319] POWER9 setting carry (and other) XER flags   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 319] POWER9 setting carry (and other) XER flags   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 320] New: split out software install and deps into separate script   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 320] split out software install and deps into separate script   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 320] split out software install and deps into separate script   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 321] New: BUG: Running ltp on a pipeline gives warnings about loops   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 321] BUG: Running ltp on a pipeline gives warnings about loops   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 319] POWER9 setting carry (and other) XER flags   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 209] spectre-proof speculative execution   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 320] split out software install and deps into separate script   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 209] spectre-proof speculative execution   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 320] split out software install and deps into separate script   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 320] split out software install and deps into separate script   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 320] split out software install and deps into separate script   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 320] split out software install and deps into separate script   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 209] spectre-proof speculative execution   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 320] split out software install and deps into separate script   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 291] HDL Workflow and Coriolis2 chroot automated setup scripts   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 291] HDL Workflow and Coriolis2 chroot automated setup scripts   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 320] split out software install and deps into separate script   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 291] HDL Workflow and Coriolis2 chroot automated setup scripts   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 266] deploy git commit-signing and tag-signing   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 209] spectre-proof speculative execution   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 266] Allow read-only git clone over https   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 322] New: deploy git commit signoff and git tag signing   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 266] Allow read-only git clone over https   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 322] deploy git commit signoff and git tag signing   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 291] HDL Workflow and Coriolis2 chroot automated setup scripts   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 266] Allow read-only git clone over https   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 320] split out software install and deps into separate script   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 320] split out software install and deps into separate script   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 320] split out software install and deps into separate script   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 320] split out software install and deps into separate script   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 291] HDL Workflow and Coriolis2 chroot automated setup scripts   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 323] New: create POWER9 MUL pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 323] create POWER9 MUL pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 324] New: create POWER9 DIV pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 323] create POWER9 MUL pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] New: create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 312] Formal Correctness Proof for CountZero needed (basically PriorityEncoder)   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 326] New: nmutil.clz to be retired (removed) because it is identical to PriorityEncoder   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 312] Formal Correctness Proof for CountZero needed (basically PriorityEncoder)   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 326] nmutil.clz to be retired (removed) because it is identical to PriorityEncoder   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 326] nmutil.clz to be retired (removed) because it is identical to PriorityEncoder   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 326] nmutil.clz to be retired (removed) because it is identical to PriorityEncoder   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 326] nmutil.clz to be retired (removed) because it is identical to PriorityEncoder   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 314] Create Condition Register pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 323] create POWER9 MUL pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 327] New: Don't use sudo with setup.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 319] POWER9 setting carry (and other) XER flags   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 319] POWER9 setting carry (and other) XER flags   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 184] new mailing lists proposal for libre-soc.org   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 328] New: move decoder RB exts function into nmutil   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 328] move decoder RB exts function into nmutil   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 70] evaluate Bus Architectures   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 70] evaluate Bus Architectures   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 329] New: coriolis2 experiment layout for Dependency Matrices   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 329] coriolis2 experiment layout for Dependency Matrices   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 329] coriolis2 experiment layout for Dependency Matrices   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 329] coriolis2 experiment layout for Dependency Matrices   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 329] coriolis2 experiment layout for Dependency Matrices   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 329] coriolis2 experiment layout for Dependency Matrices   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 329] coriolis2 experiment layout for Dependency Matrices   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 329] coriolis2 experiment layout for Dependency Matrices   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 330] New: create POWER9 Logic Pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 330] create POWER9 Logic Pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 331] New: Formal Correctness Proof for LOGICAL pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 331] Formal Correctness Proof for LOGICAL pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 331] Formal Correctness Proof for LOGICAL pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 331] Formal Correctness Proof for LOGICAL pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 198] Formal correctness proofs are needed for low-level libraries in LibreSOC   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 331] Formal Correctness Proof for LOGICAL pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 331] Formal Correctness Proof for LOGICAL pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 330] create POWER9 Logic Pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 331] Formal Correctness Proof for LOGICAL pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 332] New: Formal correctness proof needed for CR pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 70] evaluate Bus Architectures   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] New: investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 319] POWER9 setting carry (and other) XER flags   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 198] Formal correctness proofs are needed for low-level libraries in LibreSOC   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 304] Define minimum viable interface set for 180nm ASIC   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 330] create POWER9 Logic Pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 334] New: POWER decode A=zero needs to be set as a flag in Execute1Type   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 198] Formal correctness proofs are needed for low-level libraries in LibreSOC   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 331] Formal Correctness Proof for LOGICAL pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 195] Formal correctness framework is needed for Power ISA   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 335] New: Formal Correctness Proof for Branch pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 335] Formal Correctness Proof for Branch pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 195] Formal correctness framework is needed for Power ISA   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] New: add indicator to Decode2ExecuteType that RA is zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 334] POWER decode A=zero needs to be set as a flag in Execute1Type   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 328] move decoder RB exts function into nmutil   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 337] New: Convention for register outputs in *OutputData structures is to use "Data"   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 307] look at installing a kan-ban board on top of bugzilla   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 307] look at installing a kan-ban board on top of bugzilla   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 329] coriolis2 experiment layout for Dependency Matrices   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 329] coriolis2 experiment layout for Dependency Matrices   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 329] coriolis2 experiment layout for Dependency Matrices   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 338] New: CompUnitALU needs go_die to be wired to ALU shadow mask   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 338] CompUnitALU needs go_die to be wired to ALU shadow mask   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 330] create POWER9 Logic Pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 339] New: create POWER9 ROTATE pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 339] create POWER9 ROTATE pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 339] create POWER9 ROTATE pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 335] Formal Correctness Proof for Branch pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 335] Formal Correctness Proof for Branch pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 330] create POWER9 Logic Pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 335] Formal Correctness Proof for Branch pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 330] create POWER9 Logic Pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 335] Formal Correctness Proof for Branch pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 335] Formal Correctness Proof for Branch pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 335] Formal Correctness Proof for Branch pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 335] Formal Correctness Proof for Branch pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 335] Formal Correctness Proof for Branch pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 339] create POWER9 ROTATE pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 340] New: formal proof of POWER9 SHIFTROT pipeline needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 340] formal proof of POWER9 SHIFTROT pipeline needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 340] formal proof of POWER9 SHIFTROT pipeline needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 340] formal proof of POWER9 SHIFTROT pipeline needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 195] Formal correctness framework is needed for Power ISA   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 314] Create POWER9 Condition Register pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 314] Create POWER9 Condition Register pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 314] Create POWER9 Condition Register pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 314] Create POWER9 Condition Register pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 314] Create POWER9 Condition Register pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 314] Create POWER9 Condition Register pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 341] New: unit tests needed for soc.fu.compunits (shared with soc.fu.*/test_pipe_caller.py)   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 341] unit tests needed for soc.fu.compunits (shared with soc.fu.*/test_pipe_caller.py)   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 342] New: formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 342] formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 341] unit tests needed for soc.fu.compunits (shared with soc.fu.*/test_pipe_caller.py)   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 342] formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 342] formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 343] New: compalu_multi write requests need to hook into Data.ok   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 343] compalu_multi write requests need to hook into Data.ok   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 337] Convention for register outputs in *OutputData structures is to use "Data"   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 314] Create POWER9 Condition Register pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 344] New: missing mtmsr and mfsprd   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 345] New: define POWER9 regfiles   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 346] New: simplified test link between compunits and regfile   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 342] formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 331] Formal Correctness Proof for LOGICAL pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 197] Formal correctness proof needed of the 6600-style Out-of-Order execution engine   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 342] formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 335] Formal Correctness Proof for Branch pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 335] Formal Correctness Proof for Branch pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 331] Formal Correctness Proof for LOGICAL pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 347] New: add setb (to CR pipeline?)   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 314] Create POWER9 Condition Register pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 347] add setb (to CR pipeline?)   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 342] formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 342] formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 314] Create POWER9 Condition Register pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 345] define POWER9 regfiles   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 348] New: POWER9 SPR pipeline needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 348] POWER9 SPR pipeline needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 349] New: privileged-instruction decoding function needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 349] privileged-instruction decoding function needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 350] New: LDSTCompUnit also needs to support zeroing on RA   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 318] fix LDSTCompUnit   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 350] LDSTCompUnit also needs to support zeroing on RA   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 350] LDSTCompUnit also needs to support zeroing on RA   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 335] Formal Correctness Proof for Branch pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 350] LDSTCompUnit also needs to support zeroing on RA   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 350] LDSTCompUnit also needs to support zeroing on RA   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 350] LDSTCompUnit also needs to support zeroing on RA   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 351] New: create a "block" (mass) regfile port (read and write) onto an array-based regfile   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 352] New: virtual (dependency-tracked) regfile needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 342] formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 342] formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 342] formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 316] bperm TODO   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 337] Convention for register outputs in *OutputData structures is to use "Data"   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] New: formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 155] a PLL is needed for the SoC   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 155] a PLL is needed for the SoC   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 342] formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 342] formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 155] a PLL is needed for the SoC   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 155] a PLL is needed for the SoC   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 345] define POWER9 regfiles   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 354] New: idea/optimisation: make FP CMP also do INT CMP   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 354] idea/optimisation: make FP CMP also do INT CMP   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 343] compalu_multi write requests need to hook into Data.ok   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 340] formal proof of POWER9 SHIFTROT pipeline needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 343] compalu_multi write requests need to hook into Data.ok   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 343] compalu_multi write requests need to hook into Data.ok   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 348] POWER9 SPR pipeline needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 348] POWER9 SPR pipeline needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 348] POWER9 SPR pipeline needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 355] New: game theory "state" packet engine needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 355] game theory "state" packet engine needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 323] create POWER9 MUL pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 356] New: fu POWER9 pipeline unit tests need to test RA=0   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 334] POWER decode A=zero needs to be set as a flag in Execute1Type   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 350] LDSTCompUnit also needs to support zeroing on RA   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 356] fu POWER9 pipeline unit tests need to test RA=0   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 347] add setb (to CR pipeline?)   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 331] Formal Correctness Proof for LOGICAL pipeline   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 348] POWER9 SPR pipeline needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 310] Function Units to cover multiple tasks   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 357] New: create simplified (testing) version of Function Unit pipeline for test purposes   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 263] LD/ST batching needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 216] LOAD STORE buffer needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 358] New: new MCU-ALU test picked up RC / OE / CR handling issue   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 358] new MCU-ALU test picked up RC / OE / CR handling issue   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 358] new MCU-ALU test picked up RC / OE / CR handling issue   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 358] new MCU-ALU test picked up RC / OE / CR handling issue   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 359] New: cut down on wires between decode and function units   bugzilla-daemon at libre-soc.org
• [libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed   bugzilla-daemon at libre-soc.org

Last message date: Sun May 31 23:14:21 BST 2020
Archived on: Sat Jun 6 23:45:04 BST 2020

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