[libre-riscv-dev] daily kan-ban update 22may2020

[Cesar Strauss]

Em 22/05/2020 23:41, Luke Kenneth Casson Leighton escreveu:
> On Saturday, May 23, 2020, Cesar Strauss <cestrauss at gmail.com> wrote:
> 
>>
>> My motivation to participate in Libre-SOC:
>>
>> A libre, supported, fully documented SoC, free of proprietary drivers,
>> firmware and bootloaders, that I can trust to use in my workstation,
>> server and as building blocks of scientific instruments.
> 
> 
> very cool.
> 
> and even in FPGA, one that had good number crunching capability might be
> useful, i assume.
> 

If you mean, programming an FPGA board with a libre-SOC core, it would
have to be seriously optimized for size, not speed. These big FPGAs
boards are very expensive, compared to an equivalent Single Board Computer.

There is no way a relatively simple DSP algorithm, implemented on the
raw resources of an FPGA, could be beaten by a CPU/GPU core executing
this same algorithm, in the same FPGA.

Yes, people put CPU cores in FPGAs, but mainly to interface to the
outside world, providing a convenient interface to the FPGA. The main
data processing is still done in the free resources which remains after
placing the CPU core.

Of course, I could use parts of libre-SOC, like the floating points
pipelines. But, fixed-point algorithms are more common than
floating-point in FPGA applications.

Regards,

Cesar