[libre-riscv-dev] daily kan-ban update 22may2020
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sat May 23 13:08:02 BST 2020
On Saturday, May 23, 2020, Cesar Strauss <cestrauss at gmail.com> wrote:
> Of course, I could use parts of libre-SOC, like the floating points
> pipelines. But, fixed-point algorithms are more common than
> floating-point in FPGA applications.
one of the big advantages of an OoO design is the opportunity for parallel
processing interwoven cleanly behind a sequential "API" (the instruction
so let us suppose that you needed for example a significant number of fixed
point correlators, done in a specialist hardware-optimised mathematical way
that is massively inconvenient even for a DSP or a standard CPU.
however a full FPGA implementation is also inconvenient because the level
of parallelism required, when interacting closely with a sequential
program, makes the FPGA correlator a huge pain to program.
what you need would therefore be a CPU with sequential behaviour that could
just call a sequential instruction in a loop, to activate the special
custom correlator, but because that CPU is an out of order parallel
processor multiple such custom instructions (custom correlators) get issued
in parallel and the dependencies automatically resolved for you.
here you would get the best of both worlds.
another thought, for when we have time: if you can clearly express the
primitives needed, it would be a fascinating use-case evaluation to see
whether the ASIC would be any good, for the kind of DSP work that you do,
and if not, what operations would actually be needed.
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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