[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #32 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #30)

> The issue is the `rlwimi` instruction, which in addition to RS and an
> immediate also reads in RA. Because of this, I disabled putting the
> immediate into operand b in the input stage of the ALU for the RLC opcode

interesting.  am taking a closer look.  it doesn't look that different.

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