[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #33 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
i haven't committed it (i leave it to you to evaluate)
this passes the tests nosetests3 decoder/isa/test_caller.py 

register RA is read in - however it's not involved in the datapath for RB.

here's the pseudocode 

* rlwinm RA,RS,SH,MB,ME (Rc=0)
* rlwinm.  RA,RS,SH,MB,ME (Rc=1)

    n <- SH
    r <- ROTL32((RS)[32:63], n)
    m <- MASK(MB+32, ME+32)
    RA <- r & m

* rlwnm RA,RS,RB,MB,ME (Rc=0)
* rlwnm.  RA,RS,RB,MB,ME (Rc=1)

    n <- (RB)[59:63]
    r <- ROTL32((RS)[32:63], n)
    m <- MASK(MB+32, ME+32)
    RA <- r & m

the only difference is in n

both are 5 bit, SH should be coming from the immediate-decoding, (RB)[59:63]
means get the 5 LSBs of RB.

i believe we're ok making the change below.  it doesn't make sense that IBM
would design something that needs a special exception path for the immediate,
just for one instruction.


lkcl at fizzy:~/src/libreriscv/soc/src/soc$ git diff
diff --git a/src/soc/alu/input_stage.py b/src/soc/alu/input_stage.py
index 389954b..2dda52a 100644
--- a/src/soc/alu/input_stage.py
+++ b/src/soc/alu/input_stage.py
@@ -39,8 +39,7 @@ class ALUInputStage(PipeModBase):
         ##### operand B #####

         # If there's an immediate, set the B operand to that
-        with m.If(self.i.ctx.op.imm_data.imm_ok &
-                  ~(self.i.ctx.op.insn_type == InternalOp.OP_RLC)):
+        with m.If(self.i.ctx.op.imm_data.imm_ok):
             comb += self.o.b.eq(self.i.ctx.op.imm_data.imm)
         with m.Else():
             comb += self.o.b.eq(self.i.b)
diff --git a/src/soc/alu/main_stage.py b/src/soc/alu/main_stage.py
index 59c896a..173ca78 100644
--- a/src/soc/alu/main_stage.py
+++ b/src/soc/alu/main_stage.py
@@ -134,10 +134,7 @@ class ALUMainStage(PipeModBase):
                     comb += self.o.o.eq(rotl_out & mask)

             with m.Case(InternalOp.OP_RLC):
-                with m.If(self.i.ctx.op.imm_data.imm_ok):
-                    comb += rotate_amt.eq(self.i.ctx.op.imm_data.imm[0:5])
-                with m.Else():
-                    comb += rotate_amt.eq(self.i.b[0:5])
+                comb += rotate_amt.eq(self.i.b[0:5])
                 comb += maskgen.mb.eq(mb+32)
                 comb += maskgen.me.eq(me+32)
                 comb += mask.eq(maskgen.o)

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