[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #34 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://libre-soc.org/openpower/isatables/

hmmm, anton's team has synthesised the commonality between the different
rotates and shifts

https://github.com/antonblanchard/microwatt/blob/master/rotator.vhdl

back in execute1.vhdl they do this:

  right_shift <= '1' when e_in.insn_type = OP_SHR else '0';
  rot_clear_left <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type =
OP_RLCL else '0';
  rot_clear_right <= '1' when e_in.insn_type = OP_RLC or e_in.insn_type =
OP_RLCR else '0';

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