[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #35 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
i can do a brain-dead translation of this code to nmigen, tomorrow, if you're
good with that?  (i quite like doing no-brain work...)
https://github.com/antonblanchard/microwatt/blob/master/rotator.vhdl

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