[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #36 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #35)
> i can do a brain-dead translation of this code to nmigen, tomorrow, if you're
> good with that?  (i quite like doing no-brain work...)
> https://github.com/antonblanchard/microwatt/blob/master/rotator.vhdl

okok i just did it anyway :)
https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=0604fe1e0b040def2e3f599fc523340eeeefe519

i cut out the hand-coded ROTL and replaced it with... ROTL.

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