[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon May 11 00:11:51 BST 2020


--- Comment #31 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
these would be better (again) as (sigh) add(x,y) etc.  sub(63, n) rather than

also if the use of EXTZ64 *really* is necessary, that's actually a bug in the
rather than something that we should arbitrarily fix, and it should be

@@ -168,9 +168,9 @@
     def op_slw(self, RB, RS):
         n = RB[59:64]
-        r = ROTL32(RS[32:64], n)
+        r = ROTL32(EXTZ64(RS[32:64]), n.value)
         if eq(RB[58], 0):
-            m = MASK(32, 63 - n)
+            m = MASK(32, 63 - n.value)
             m = concat(0, repeat=64)
         RA = r & m

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