[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #30 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #29)
> https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/alu/main_stage.py;
> hb=HEAD#l137
> 
> i'm fairly certain that this:
> 
>  136             with m.Case(InternalOp.OP_RLC):
>  137                 with m.If(self.i.ctx.op.imm_data.imm_ok):
>  138                     comb +=
> rotate_amt.eq(self.i.ctx.op.imm_data.imm[0:5])
>  139                 with m.Else():
>  140                     comb += rotate_amt.eq(self.i.b[0:5])
> 
> can just be this:
> 
>  136             with m.Case(InternalOp.OP_RLC):
>  137                 comb += rotate_amt.eq(self.i.b[0:5])
> 
> because in input_stage.py there is this:
> 
>   40         # If there's an immediate, set the B operand to that
>   41         with m.If(self.i.ctx.op.imm_data.imm_ok):
>   42             comb += self.o.b.eq(self.i.ctx.op.imm_data.imm)
>   43         with m.Else():
>   44             comb += self.o.b.eq(self.i.b)

The issue is the `rlwimi` instruction, which in addition to RS and an immediate
also reads in RA. Because of this, I disabled putting the immediate into
operand b in the input stage of the ALU for the RLC opcode

-- 
You are receiving this mail because:
You are on the CC list for the bug.