[libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Fri May 15 21:11:05 BST 2020


--- Comment #10 from Michael Nolan <mtnolan2640 at gmail.com> ---
diff --git a/src/soc/branch/pipe_data.py b/src/soc/branch/pipe_data.py
index cab43cf..6d97102 100644
--- a/src/soc/branch/pipe_data.py
+++ b/src/soc/branch/pipe_data.py
@@ -22,10 +22,11 @@ class BranchInputData(IntegerData):
         # We need both lr and spr for bclr and bcctrl. Bclr can read
         # from both ctr and lr, and bcctrl can write to both ctr and
         # lr.
+        self.tar = Signal(64, reset_less=True) # Target Address Register

I removed the TAR input, because the branch instruction would need to decide
which of the 3 inputs to branch to. Instead, it should be fed that operand in
the spr input (though that does mean it will be fed ctr twice for bcctr...).
Does that seem reasonable?

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