[libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=313

--- Comment #35 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #34)

> however for the purposes of this discussion, the LSBs/MSBs i *believe*
> is as simple as hard-wiring the ordering correctly on the 32-bit path.
> 
> * all 8 4-bit read/writes *at the regfile*, to produce the full 32-bit CR,
>   will be LSB/MSB *hard-wired* correctly, right there.
> 
> 
> so with that in mind, would i be correct in thinking that the CR Regfile
> actually needs to store the data as:
> 
> CR0: bit 3 2 1 0 CR1: 7 6 5 4 CR2: 11 10 9 8
> 
> ?

I think it'll actually be

CR0: bit 0 1 2 3 CR1: 4 5 6 7 CR2: 8 9 10 11

but it'll need some testing to be sure.

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