[libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=313

--- Comment #34 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #33)
> (In reply to Luke Kenneth Casson Leighton from comment #32)
> > > then in OP_BC look up the remaining 2 bits of BI to select which bit of CRn
> > > is to be used, right?
> > 
> > (2 LSBs)
> 
> Yep, that's the idea!

excccellent, muhahaha oopssorry.

> I think the register file should be designed to address the 8 crs in the
> correct bit order. If I ask for cr0, I should get cr0, whether cr0 comes
> from the 4 lsbs of the full register, or the 4 msbs.

sigh.  i will need help when it comes to that.  i will have no clue which
way round.

basically i believe it may be quite simple... but this is POWER.

* the CR regfile will be subdivided into 8 separate latch-banks (not a
  standard SRAM, at all)

* there will be 8 read-enable (and write-enable) lines.

* it will be possible to read/write *all* of those simultaneously to obtain
  the full 32-bit CR.  this on a 32-bit data path

* it will also be possible to read/write individual 4-bit CRs by a single
  read/write-enable line.  this on a 4-bit data path

the DMs take care of ensuring that 32 and 4 bit read/writes are entirely
mutually exclusively time-sliced.

however for the purposes of this discussion, the LSBs/MSBs i *believe*
is as simple as hard-wiring the ordering correctly on the 32-bit path.

* all 8 4-bit read/writes *at the regfile*, to produce the full 32-bit CR,
  will be LSB/MSB *hard-wired* correctly, right there.


so with that in mind, would i be correct in thinking that the CR Regfile
actually needs to store the data as:

CR0: bit 3 2 1 0 CR1: 7 6 5 4 CR2: 11 10 9 8

?

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