[libre-riscv-dev] daily kan-ban update 18may2020
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Mon May 18 12:45:26 BST 2020
over the weekend i:
* continued to help michael with the pipelines (and moved them to
soc.fu this morning).
* also helped cole.
* and a new team member cesar (welcome!).
* and got LDSTCompUnit working (maybe).
* and had a fascinating conversation thanks to yehowshua and jeremy
(also welcome!), which resulted in this
* and did a preliminary first cut at a pinmux for the 180nm chip.
* and probably some other things i've forgotten about as i was up late
enough that my neuro-electrical memory is slightly shot.
* also this morning i reviewed the XER register and added some tables
from p45-6 of V3.0B spec to determine when the bits are set.
documented here https://libre-soc.org/openpower/pipeline_operands/
this latter is going to be a bit of a pig. if we don't treat the XER
bits - each *bit* - as an actual separate and distinct "register" -
protected by a Dependency Matrix column - we might as well give up -
and no, doing an in-order design will not help on any level of
performance because all of those operations which set XER bits *still*
need to stall. microwatt only gets away with this because it is only
a 2-stage pipeline.
today i will see how it goes because am still recovering from the
effects of three disrupted sleep nights in a row.
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