[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #44 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
see this (yes it's LD/ST not an ALU)
https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg

you see how Op2 (RB) is selected through a mux, based on the Imm/Opcode?
the ALU (the weird "boat" symbol) doesn't get to make the decision, it
gets "told".

however if you follow the "imm_ok" wire from the Imm/Opcode latch, you'll
see it PREVENTS REQ_RD2 from even being activated, when "imm_ok" is true.

this is the primary purpose (role) of the Computation Units: make requests
for Register File Ports *that are needed*.

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