[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #56 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
you probably noticed, i split out Logical operations into a separate
pipeline, mirroring logical.vhdl
https://github.com/antonblanchard/microwatt/blob/master/logical.vhdl

popcount, parity, i've added TODO.

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