[libre-riscv-dev] [Bug 314] New: Create Condition Register pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=314

            Bug ID: 314
           Summary: Create Condition Register pipeline
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Mac OS
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

we need a Condition Register pipeline
https://github.com/antonblanchard/microwatt/blob/master/execute1.vhdl
https://libre-soc.org/openpower/isa/condition/

* OP_MFCR
* OP_CROP (which includes MCRF)
* OP_MTCRF

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