[libre-riscv-dev] daily kan-ban 07may2020 update
staf at fibraservi.eu
Fri May 8 09:41:02 BST 2020
Luke Kenneth Casson Leighton schreef op vr 08-05-2020 om 03:26 [+0100]:
> On Friday, May 8, 2020, Jacob Lifshay <programmerjake at gmail.com> wrote:
> > I attended the OpenPower virtual coffee meeting, there was an interestingsuggestion to see if we could move to a later tapeout than october, toavoid burnout due to deadline crunch.
> i've written to Staf to see what is available. if you recall we have anagreement to let him use the Oct2020 slot. so he is "2nd in queue".
> there were other ideas to do a simpler processor for that slot. howeverthese would likely go to the *back* of the queue (as a new request for thatslot: "3rd in queue").
As a backup plan I had in mind to tape-out some other CPU like a SwerV RISC-V core from Western Digital. Alternatively some of the budget could be used so I can look into multi-port RAMs and register files; maybe I can have a closer look at a PLL also. These could first be tested on 0.35um which costs a lot less (ca. $5000 vs. ca $20000).
There is question about funding. It takes about 3 months after tape-out to get the chips and then the debugging of the chip can only begin which typically also takes a lot of time. So if we delay the tape-out the completion of the testing of the chip will miss the deadline for the current NLNet funding. I am currently supposed to do the testing of the chip but I won't start that if I don't know if I can get the funding for it.
0.18um TSMC MPW runs are done at least once a month. You can find the schedule online: https://europractice-ic.com/wp-content/uploads/2020/05/General-MPW-EUROPRACTICE-200505-v8.pdf
So last two tape-out dates this year are 18/11 and 2/12 (I think 2/12 was not there in a previous version of the file).
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