[libre-riscv-dev] Finished Scoreboard
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Tue May 5 17:26:14 BST 2020
On Tue, May 5, 2020 at 5:15 PM Yehowshua <yimmanuel3 at gatech.edu> wrote:
> Do you think the scoreboard can be done by mid June?
i'm assuming you meant to ask this on the list.
the actual scoreboard (dependency matrices) themselves are "done". it
was only the change to multi-signal control at the register file that
needed alteration, and *that* was done several weeks ago (didn't take
it's the "arbitration" connectivity to the register file (3 days
design work on the cyclic buffer system), the LDSTCompUnit (10 days
redesign, 2-3 days implementing, the change to the ALU CompUnit (8
days redesign, 2-3 days implementing) that is the time-sink.
the next phase is to create a POWER9 "Condition" Register File
containing CR0-CR7, CTR and other essential registers related to
Branch Control. this *extra register file* was the primary motivation
behind the additional scoreboard read/write "operand" wires, because
one set manages the INT/FP regfile, another set manages the "Condition
Register" regfile (oh, and another set - with a completely different
DM Matrix - manages the SPRs.
which is why we need people to focus on "ancillary" tasks because
without people focussing on ancillary tasks, we're not going to have
instructions completed, the pipelines designed, the memory interface
completed, no Branch Prediction Unit, no TLB, no RADIX MMU.
hence the urgency of asking people to focus on specific tasks, and not
the amount that we have to do in such a short amount of time is
enormous, and we need to bash through it, without wasting *any* time.
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