[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #38 from Michael Nolan <mtnolan2640 at gmail.com> ---
Ugh. I added support to the alu testbench for reading the registers specified
in the instruction, instead of hardcoding them to 1, 2, and 3. I have it read
the register select ports in the decoder in the order [3, 1, 2], and the first
2 with valid data end up in the a and b inputs of the ALU. I'm a bit annoyed
about the weird order, but everything seems to work

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