[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #39 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #37)

> Look at rlwimi:
> 
> n <- SH
> r <- ROTL32(RS[32:63], n)
> m <- MASK(MB+32, ME+32)
> RA <- r & m | (RA) & ~m
> 
> It definitely does require reading in RS, RA, and SH

that's ok - yes it reads RS, RA and SH. what it doesn't do is need to
switch off RB imm decoding.  at least, let me put it this way:
the unit test passes fine with that patch.

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