[libre-riscv-dev] [Bug 208] implement CORDIC in a general way sufficient to do transcendentals

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Tue May 5 15:55:26 BST 2020


--- Comment #42 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #40)
> Luke, your latest commit (74af221) breaks the tests for the pipelined fpsin:

yep i commented it out for now (and explained why!)

> ======================================================================
> ERROR: test_rand (__main__.SinCosTestCase)
> ----------------------------------------------------------------------
> Traceback (most recent call last):
>   File "test_fp_pipe.py", line 80, in test_rand
>     self.run_test(iter(inputs), outputs=iter(outputs))
>   File "test_fp_pipe.py", line 21, in run_test
>     vl = rtlil.convert(dut, ports=dut.ports())
>   File
> "/home/mnolan/.local/lib/python3.8/site-packages/nmigen/back/rtlil.py", line
> 1017, in convert
>     fragment = ir.Fragment.get(elaboratable, platform).prepare(**kwargs)
>   File "/home/mnolan/.local/lib/python3.8/site-packages/nmigen/hdl/ir.py",
> line 540, in prepare
>     raise TypeError("Only signals may be added as ports, not {!r}"
> TypeError: Only signals may be added as ports, not (slice (sig x) 0:1)
> It looks like dut.ports() is returning a bunch of slices for the output
> signals and I'm not sure why:

yep it means that in the data_i or data_o you've missed a "yield from"
and used "yield" instead.  or vice-versa.

"yield from x" would iterate *through x* and that tells nmigen "please
return slices of single-bits of x".

i'll take a look

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