[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon at libre-soc.org
bugzilla-daemon at libre-soc.org
Thu May 14 17:54:25 BST 2020
https://bugs.libre-soc.org/show_bug.cgi?id=305
--- Comment #63 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #59)
> *headdesk*
move the keyboard to the left, first...
> cmp is BACKWARDS!
:)
> (gdb) p/x $r1
> $1 = 0x40000000
> (gdb) p/x $r2
> $2 = 0x80000000
are ya having fun, yet?
> Why IBM, why did you do this?
hm i dunno... i mean... it could be justified if it's less code to check
+ve condition quicker than it is to check -ve condition or vice-versa.
then you would use sub for one and cmp for the other.
honestly: am clueless :)
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