[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #64 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #63)

> honestly: am clueless :)

ah i think i might know why.  as we found out in the PartitionedSignal
GT / LT (etc) code, a comparator is much simpler than a full adder.

it's only *because* we are using the output from the adder (actually,
subtracter) - purely because it's there - that we're noticing the
inversion.

if however we had a totally separate Function Unit for CMP, we'd use
the less-gates solution, and consequently could swap A and B over.
then you'd never notice the difference :)

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