[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu May 14 18:29:15 BST 2020


--- Comment #65 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #64)
> (In reply to Luke Kenneth Casson Leighton from comment #63)
> > honestly: am clueless :)
> ah i think i might know why.  as we found out in the PartitionedSignal
> GT / LT (etc) code, a comparator is much simpler than a full adder.
> it's only *because* we are using the output from the adder (actually,
> subtracter) - purely because it's there - that we're noticing the
> inversion.
> if however we had a totally separate Function Unit for CMP, we'd use
> the less-gates solution, and consequently could swap A and B over.
> then you'd never notice the difference :)

That makes a little more sense. Though if they're going to the trouble of
making subf the way it is, you'd think they'd make this the same way. 

Oh well

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