[libre-riscv-dev] [Bug 318] fix LDSTCompUnit

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=318

--- Comment #15 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cesar Strauss from comment #14)
> Dear Luke,
> 
> I see uses of "latchregister" and "SRLatch" in code. In the nMigen library,
> they are internally implemented with synchronous logic, although partly
> resembling the function of their asynchronous equivalents.

yes.  this was the best i could think of that is reasonably close and at the
same time is verifiable if we went with standard commercial tools.

SR NAND most definitely is not verifiable except with proprietary tools that
are rented at USD 250,000 a week.

> 
> Do you, by any chance, intend to replace them, in the ASIC, with real
> asynchronous latches?

for the CompUnits, probably not.  the gate count (number of SRLatch instances)
is not high enough to justify the risk.

> As depicted in several diagrams at
> https://libre-soc.org/3d_gpu/architecture/6600scoreboard/ ?

yes.  i kept these to make it possible to understand the relationship with what
Mitch taught me.

however you have to appreciate that the 6600 diagrams worked by alternating low
and high clock cycles.

in particular, the Dependency Matrix cells very specifically activate "issue"
on the HI cycle and clear GOREAD on i believe the LO cycle.

i decided that sticking closely to this as a very first chip might not be a
good idea, although it is extremely cool.

consequently instead i created SRLatch and then used a sync on resetting it as
the "primary method" of responding to REQUEST signals.

you will therefore see a GO signal be the reset driver on for example the read
latch, as a *sync* not a comb.

this leaves the SRLatch latch open for precisely one clock cycle, and the
corresponding REQ, generated from the Q of the SRlatch instance, will then
drop.  which is exactly what is needed to capture the incoming data.

remember, GOREAD is only set (and set for only one cycle) when the Regfile Bus
is svailable to transport data to this Unit.

a standard design (wishbone) would use ready/valid signalling to do exactly the
same thing, it is just different names.

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