[libre-riscv-dev] LD/ST Comp Unit FSM (was: Re: Scoreboard vs Tomasulo)
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sun May 17 11:07:19 BST 2020
On Sun, May 17, 2020 at 6:25 AM Cesar Strauss <cestrauss at gmail.com> wrote:
> > https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg
> > this i reaaaally need some help with.
> I'm willing to lend a hand in this, and/or any other tasks the group
> deem appropriate.
that's really appreciated, Cesar.
> Do you have already have any code, unit test and/or testbench for this
> module? A timing diagram would also be welcome.
yes, it's here:
the timing diagram is auto-generated when running that code (as its
own unit test: python3 experiment/compldst_multi.py). it can be
loaded with "gtkwave". to save you some time adding 100+ signals to
gtkwave i'm attaching a pre-saved diagram, i even set some pretty
colours in it :)
also a second one for the L0 cache/buffer to which CompLDSTUnit is
connected. this is run as "python3 experiment/l0_cache.py"
i will raise a bugreport about it as this should be discussed there.
> Regarding myself, I do have experience in digital circuit design, and
> finite state machines in particular, which I mostly apply to FPGA
> My field of work is in data acquisition and control, for scientific
> instruments, at the astrophysics department of a research institute (but
> I am an engineer, not an astronomer). I apply microcontrollers and FPGAs
> at several research projects. With the rise of single-board computers,
> I'm starting to use them as well.
> My main attraction to this project is having free firmware and boot
> loaders, and also full documentation, freely available and complete, by
that's really appreciated.
> I have read the Charter at https://libre-soc.org/charter/, and agree
> with it.
thank you Cesar.
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