[libre-riscv-dev] LD/ST Comp Unit FSM (was: Re: Scoreboard vs Tomasulo)
cestrauss at gmail.com
Sun May 17 13:59:26 BST 2020
Em 05/17/2020 07:07, Luke Kenneth Casson Leighton wrote:
> On Sun, May 17, 2020 at 6:25 AM Cesar Strauss <cestrauss at gmail.com> wrote:
>>> this i reaaaally need some help with.
>> I'm willing to lend a hand in this, and/or any other tasks the group
>> deem appropriate.
> that's really appreciated, Cesar.
I'm glad I can help.
>> Do you have already have any code, unit test and/or testbench for this
>> module? A timing diagram would also be welcome.
> yes, it's here:
> the timing diagram is auto-generated when running that code (as its
> own unit test: python3 experiment/compldst_multi.py). it can be
> loaded with "gtkwave". to save you some time adding 100+ signals to
> gtkwave i'm attaching a pre-saved diagram, i even set some pretty
> colours in it :)
> also a second one for the L0 cache/buffer to which CompLDSTUnit is
> connected. this is run as "python3 experiment/l0_cache.py"
> i will raise a bugreport about it as this should be discussed there.
I saw it (https://bugs.libre-soc.org/show_bug.cgi?id=318). I'll assign
it to myself then, if you don't mind?
I think I have enough information available, to proceed. I'm beginning
already to have some understanding of the problem at hand. I'll ask if
I need anything. I'll give feedback as I go on.
I've been following the mailing list for some time, with interest, but
skimming over more technical details. I'll try to become more up to speed.
I did attend an introductory course on Computer Architecture, so I do
have a little background on the subject.
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