[libre-riscv-dev] LD/ST Comp Unit FSM (was: Re: Scoreboard vs Tomasulo)
cestrauss at gmail.com
Sun May 17 06:24:54 BST 2020
On 05/16/2020 21:53, Luke Kenneth Casson Leighton wrote:
> because POWER9 has in some cases up to *five* incoming registers and
> *three* outgoing registers (in different Regfiles - INT/FP, SPR, CR), we needed
> to split those out into individual lines. GO-READ1/READ-REQ1,
> GO-READ2/READ-REQ2 etc.
> currently i am struggling with this FSM which implements 3-operand in,
> immediates, 2-operand out *and* manages the address, GO-ST, address
> exceptions and deals with POWER9 LD/ST "Update" mode.
> this i reaaaally need some help with.
I'm willing to lend a hand in this, and/or any other tasks the group
Do you have already have any code, unit test and/or testbench for this
module? A timing diagram would also be welcome.
Regarding myself, I do have experience in digital circuit design, and
finite state machines in particular, which I mostly apply to FPGA
My field of work is in data acquisition and control, for scientific
instruments, at the astrophysics department of a research institute (but
I am an engineer, not an astronomer). I apply microcontrollers and FPGAs
at several research projects. With the rise of single-board computers,
I'm starting to use them as well.
My main attraction to this project is having free firmware and boot
loaders, and also full documentation, freely available and complete, by
I have read the Charter at https://libre-soc.org/charter/, and agree
I can use only my free time (weekends and evenings).
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