[libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=324

--- Comment #3 from Jacob Lifshay <programmerjake at gmail.com> ---
after looking through the spec some, it turns out that div and rem don't
actually trap on division by zero, so that makes them much easier to implement.
The numerical results are undefined on division-by-zero/overflow, so I will
need to run some tests on a Power processor to see which results we should
produce, hopefully they are the same as for RISC-V.

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