[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #23 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---

 255         # all request signals gated by busy_o.  prevents picker problems
 256         m.d.comb += self.busy_o.eq(opc_l.q) # busy out
 257         bro = Repl(self.busy_o, self.n_src)
 258         m.d.comb += self.rd.rel.eq(src_l.q & bro) # src1/src2 req rel
 259 

ah.

right.

try this, at line 258

sls = []
for l in sl:
   sls.append(l[2]) # get latch conditions
self.rd.rel.eq(Cat(*sls) & bro)

that is bringing in the immediate selection.  i think.  from the muxes.

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