[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon May 25 02:19:55 BST 2020


--- Comment #22 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cesar Strauss from comment #21)

> Just a reminder that the FSM still needs adjustment for rd.rel/rd.go.
> Checked in GTKWave that rd.rel is still being set unconditionally after
> issue_i.

if rd.rel[0] is being set when zero_a is on, yes that's bad.

rd.go[N] is an external response to rd.req[N].  this is why it is critical to
get rd.req and wr.req bits set right because the external user of the CompUnits
kniws nothing about *why* they are set, they just respond.

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-riscv-dev mailing list