[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #22 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cesar Strauss from comment #21)

> Just a reminder that the FSM still needs adjustment for rd.rel/rd.go.
> Checked in GTKWave that rd.rel is still being set unconditionally after
> issue_i.

if rd.rel[0] is being set when zero_a is on, yes that's bad.

rd.go[N] is an external response to rd.req[N].  this is why it is critical to
get rd.req and wr.req bits set right because the external user of the CompUnits
kniws nothing about *why* they are set, they just respond.

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