[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon May 25 02:31:48 BST 2020


--- Comment #24 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
m.d.comb += src_sel.eq(Mux(op_is_imm, self.opc_l.q, self.src_l.q[i]))
sl[i][2] = src_sel

hmm you see how that interacts, from the src_srl?

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-riscv-dev mailing list