[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #24 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
m.d.comb += src_sel.eq(Mux(op_is_imm, self.opc_l.q, self.src_l.q[i]))
sl[i][2] = src_sel

hmm you see how that interacts, from the src_srl?

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