[libre-riscv-dev] [Bug 334] New: POWER decode A=zero needs to be set as a flag in Execute1Type

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=334

            Bug ID: 334
           Summary: POWER decode A=zero needs to be set as a flag in
                    Execute1Type
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_decoder2.py;h=3b9beba954a2f0f7ebefc7a731d8eddcb3705698;hb=HEAD

detection of zero RA reg needs to be passed through the CompUnits just as B
being used as an immediate.

this therefore needs to be done in the unit tests, qemu to check the
simulation, then HDL unit tests detect RA_OR_ZERO and likewise set A to zero.

a flag "a_is_zero" or such would be set in power_decode2 in the execute phase.

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