[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=296

--- Comment #9 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://groups.google.com/d/msg/comp.arch/qeMsE7UxvlI/t6QtE4C2AQAJ

idea: one cyxlic buffer *at every FunctionUnit* and turn the buses into general
data buses.

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