[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Wed May 27 17:06:19 BST 2020


--- Comment #83 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
um... um... it just occurred to me: if we detect that XER sticky overflow
is 1 in the ALU output stage, and if it is set (and required - insn.OE etc.)
only then do we even request a write to the XER.so register, then because
it is only setting, i do not believe we even need to read the XER.so at all.

as in: i think we can actually *remove* XER.so from ALUInputData, entirely.

this is because we don't actually care what the former value was - at all -
we are merely setting it.  and because that new value is *not* dependent
on the old value - at all - we don't need to waste that read port.

does this sound like a reasonable analysis?

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