[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #6 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ok done for imm_data, here is the location, it is virtually a cookie-cut of
what
is done for imm_data, bear in mind it will need to be src_l.q[0] and because
src_l.q[0] covers RA, where src_l.q[1] covers RB.  likewise the src1_or_imm
needs to go into sl[0] not sl[1]


```
        # if the operand subset has "zero_a" we implicitly assume that means
        # src_i[0] is an INT register type where zero can be multiplexed in,
instead.
        # see https://bugs.libre-soc.org/show_bug.cgi?id=336
        #if hasattr(oper_r, "zero_a"):
            # select zero immediate if opcode says so.  however also change the
latch
            # to trigger *from* the opcode latch instead.
            # ...
            # ...

        # if the operand subset has "imm_data" we implicitly assume that means
        # "this is an INT ALU/Logical FU jobbie, RB is multiplexed with the
immediate"
        if hasattr(oper_r, "imm_data"):
            # select immediate if opcode says so.  however also change the
latch
            # to trigger *from* the opcode latch instead.
            op_is_imm = oper_r.imm_data.imm_ok
```

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