[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
    bugzilla-daemon at libre-soc.org 
    bugzilla-daemon at libre-soc.org
       
    Sat May 23 13:51:01 BST 2020
    
    
  
https://bugs.libre-soc.org/show_bug.cgi?id=336
--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
Cesar, hi,
just to let you know, this should *not* interfere with adding is_zero support. 
it however will be necessary to use this:
    if hasattr(self.oper_i, "zero_a"):
        # ok now we know that this operation requires zero_a support, we can    
        # mux in zero_a.  otherwise we must put register a straight through
i am doing a minor code-morph on MultiCompUnit which makes it suitable for
general use across multiple pipelines, as specified by "regspecs".  an example
is below.
note that this example - which uses CompCROpSubset **NOT** CompALUOpSubset -
is why we will need the "detection" above.
please do not let this stop you from adding zero_a detection support, let us
keep in touch and coordinate here.
i will have to add "detect if there is an operand B immediate" in the same way,
so you can see how it is done.
class CompCROpSubset(Record):
    def __init__(self, name=None):
        layout = (('insn_type', InternalOp),
                  ('fn_unit', Function),
                  ('insn', 32),
                  ('read_cr_whole', 1),
                  ('write_cr_whole', 1),
                  )
class CRInputData(IntegerData):
    regspec = [('INT', 'a', '0:63'),      # 64 bit range
               ('INT', 'b', '0:63'),      # 6B bit range
               ('CR', 'full_cr', '0:31'), # 32 bit range
               ('CR', 'cr_a', '0:3'),     # 4 bit range
               ('CR', 'cr_b', '0:3'),     # 4 bit range
               ('CR', 'cr_c', '0:3')]     # 4 bit range
class CROutputData(IntegerData):
    regspec = [('INT', 'o', '0:63'),      # 64 bit range
               ('CR', 'full_cr', '0:31'), # 32 bit range
               ('CR', 'cr_o', '0:3')]     # 4 bit range
    ...
class CRPipeSpec(CommonPipeSpec):
    regspec = (CRInputData.regspec, CROutputData.regspec)
    opsubsetkls = CompCROpSubset
-- 
You are receiving this mail because:
You are on the CC list for the bug.
    
    
More information about the libre-riscv-dev
mailing list