[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #4 from Cesar Strauss <cestrauss at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #3)
> (In reply to Cesar Strauss from comment #2)
> > Dear Luke,
> > 
> > Please do not bother drawing a gate level diagram for the FSM. Your
> > description is enough.
> 
> we need one for the documentation, which is an extremely important aspect of
> this project.

I agree, documentation is essencial.

But I argue that a diagram that shows too much detail, and goes all the way to
gate level, is more like source code than documentation.

> plus i find it very difficult to think of timing related designs without a
> gate level drawing.
> 
> as in i literally can't write these FSMs without one (!)

Sure, I understand. It's just practice, and realizing the convenience.

At the start, I used to input all my FPGA designs with a schematics editor. The
FPGA library actually had blocks for many of the 74XX logic family parts.

Then, as I learned about VHDL, I started translating some of my previous
designs to it.

Eventually, I got so used to it, that I started writing VHDL directly. It's so
much more compact, so less tangled wires, so less time spent arranging the
symbols around the page.

Lastly, I learned about Verilog, and switched to it for its simplicity.

> > For the dataflow (registers, ALU, muxes), yes, a diagram is useful, but do
> > represent the whole FSM as an empty box.
> > 
> > I find that I can better design an FSM by starting from a behavioral
> > description,
> 
> then comment 1 should do the trick?

Yes, it's all I need.

Regards,

Cesar

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