[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu May 21 22:41:39 BST 2020


--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cesar Strauss from comment #2)
> Dear Luke,
> Please do not bother drawing a gate level diagram for the FSM. Your
> description is enough.

we need one for the documentation, which is an extremely important aspect of
this project.

plus i find it very difficult to think of timing related designs without a gate
level drawing.

as in i literally can't write these FSMs without one (!)

this one is wrong (imm needs muxing)

the imm mux path in this one is correct

immed mode hooks RD_REQ2, switching it off.

> For the dataflow (registers, ALU, muxes), yes, a diagram is useful, but do
> represent the whole FSM as an empty box.
> I find that I can better design an FSM by starting from a behavioral
> description,

then comment 1 should do the trick?

RD_REQ1 (rd.req[0]) needs to be disabled if oper_i.zero_a is set, and src_i[0]
set to zero in all 64 bits.

> preferably in the form of a timing diagram.

i am used to examining those, drawing them not so much.

> If you like, you can draw one in paper, of what you want to see in the
> GTKWave window. With arrows linking what edge causes which transition in
> another signal.
> What do you think?

i can give it a shot once i am confident with the gate level.

are you ok to go via the description for now?

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