[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #7 from Cesar Strauss <cestrauss at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #6)
> ok done for imm_data, here is the location, it is virtually a cookie-cut of
> what
> is done for imm_data, bear in mind it will need to be src_l.q[0] and because
> src_l.q[0] covers RA, where src_l.q[1] covers RB.  likewise the src1_or_imm
> needs to go into sl[0] not sl[1]

I have done the above. I held my commit because you seemed to be working on the
file. It's OK to commit now?

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