[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sat May 23 20:16:28 BST 2020


--- Comment #8 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cesar Strauss from comment #7)
> (In reply to Luke Kenneth Casson Leighton from comment #6)
> > ok done for imm_data, here is the location, it is virtually a cookie-cut of
> > what
> > is done for imm_data, bear in mind it will need to be src_l.q[0] and because
> > src_l.q[0] covers RA, where src_l.q[1] covers RB.  likewise the src1_or_imm
> > needs to go into sl[0] not sl[1]
> I have done the above.


> I held my commit because you seemed to be working on the file.

yeh don't do that: just shove it in :)

> It's OK to commit now?

git pull to merge, first, then go for it.  i happen to just be going out

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-riscv-dev mailing list