[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu May 21 11:31:40 BST 2020


--- Comment #82 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
apologies, michael, i've introduced a bug somewhere in ALU:

adde. 5, 6, 7
['RA', 'RB']
reading reg 6
reading reg 7
[SelectableInt(value=0xc97cd5181acb17fc, bits=64),
SelectableInt(value=0x9de943b0d85daaf9, bits=64)]
(SelectableInt(value=0x676618c8f328c2f6, bits=64),)
concat 1 SelectableInt(value=0x4, bits=4)
[SelectableInt(value=0x1, bits=1), SelectableInt(value=0x1, bits=1)]
__eq__ SelectableInt(value=0x0, bits=1) SelectableInt(value=0x1, bits=1)
__eq__ SelectableInt(value=0x0, bits=1) SelectableInt(value=0x1, bits=1)
writing reg 5 SelectableInt(value=0x676618c8f328c2f6, bits=64)
expected 676618c8f328c2f6, actual: 676618c8f328c2f6

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