[libre-riscv-dev] [Bug 314] Create POWER9 Condition Register pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=314

--- Comment #22 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #21)
> unit test is not testing reg output (MFCRF, ISEL)

now it is...

commit c2a94b3e640c6c3a8e33834f8d073c795ce66815 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Sun May 24 21:46:56 2020 +0100

    add test of reg output, for MFCRF and ISEL

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