[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon at libre-soc.org
bugzilla-daemon at libre-soc.org
Wed May 27 19:38:26 BST 2020
https://bugs.libre-soc.org/show_bug.cgi?id=305
--- Comment #88 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #87)
> sounds good. In my very limited experience with disassembling Power code,
> compilers don't usually enable Rc or overflow writing.
that meshes with observations that the spec says performance is adversely
affected.
--
You are receiving this mail because:
You are on the CC list for the bug.
More information about the libre-riscv-dev
mailing list