[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #88 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #87)

> sounds good. In my very limited experience with disassembling Power code,
> compilers don't usually enable Rc or overflow writing.

that meshes with observations that the spec says performance is adversely
affected.

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