[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #87 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #86)
> i think the best we can do is, when Rc=0, disable reading of XER.so
> 
> Rc=1 basically makes a hell of a mess of the dependencies.

sounds good. In my very limited experience with disassembling Power code,
compilers don't usually enable Rc or overflow writing.

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