[libre-riscv-dev] little-endian only power cores and spec compliance

[Jacob Lifshay]

Over on Libre-SOC's mailing list (CCed), we've been having a conversation
about the newly-released spec v3.1 and the compliance levels:
http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006502.html

we are building a cpu that is intended to be Linux capable, however doesn't
support Power's SIMD instructions and is LE only. We've been running into
an issue with the spec's compliance levels:
the linux compliance level requires SIMD and BE is optional but the lower
compliance levels require BE but SIMD is optional.

Would it be possible to get a LE version of the int and int+float
compliance levels added to the spec?

Other ideas also welcome

Jacob Lifshay