[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sat May 9 19:23:58 BST 2020


--- Comment #21 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
hiya michael i deployed a trick that was used in the PartitionedAdder.
rather than use 2 separate adds, A and B are shifted up by 1 bit, then
you put a 1 into A[0] and the carry into B[0].  that way you do a 66
bit add, discard bit 0, result is bits 1-64, and carry is the MSB.

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-riscv-dev mailing list