[libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu May 21 20:22:24 BST 2020


--- Comment #24 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
this creates a false (unnecessary) dependency, where cr_c would need to be
read on every OP_CR* operation, and "passed through".  the idea is to
enable cr_o.ok for instances where it's needed.

or, are there *really* operations that need 3 4-bit CRs as input?  i
don't believe so

@@ -53,9 +53,6 @@ class CRMainStage(PipeModBase):
         cr_b_arr = Array([cr_b[i] for i in range(4)])
         cr_o_arr = Array([cr_o[i] for i in range(4)])

-        comb += cr_o.eq(cr_c)
         with m.Switch(op.insn_type):
             ##### mcrf #####
             with m.Case(InternalOp.OP_MCRF):

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