[libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog

[Michael Nolan]

On 5/13/20 2:18 PM, Luke Kenneth Casson Leighton wrote:
> that's the simple version (and a cool one), i was thinking in terms of a
> suite of single-bit full adders that then need to be manually linked up.
>
> in verilog or vhdl this is a total pain.
>
I agree it's easier to do in nmigen, but both verilog and vhdl support 
generate statements for doing just that.

module wide_adder(o, a, b);
    input [8:0] a;
    input [8:0] b;
    output [8:0] o;

    genvar     i;

    wire [9:0]     carries;
    assign carries[0] = 0;

    generate
       for(i=0; i<9; i=i+1) begin
      adder u0 (.o(o[i]), .carry_out(carries[i+1]),
            .a(a[i]), .b(b[i]),
            .carry_in(carries[i]));
       end
    endgenerate
endmodule

--Michael